1. Technical Field
The present invention relates in general to digital computer systems and more particularly to a digital computer system that allows individual elements or processors to perform high-speed, low latency communications with each other in a parallel fashion over switching networks.
2. Description of the Related Art
Multistage switching networks are well known in the art and are used for interconnecting multiple devices within a digital data computer processing system. In particular, a typical networking system may use a multistaged switching network to interconnect n system elements, where n can be any number of processors or combinations of processors and other system elements.
Current state of the art switching systems have several problems, which include: expense, slow operation speed, lack of expandability, difficulty in reconfiguring, serial in nature, and clock synchronization. Thus, it is important to seek out characteristics in the medium that include fast access arbitration, fair arbitration (i.e., no unit is starved for access), independence of connections, deadlock prevention, equal opportunity for a processor to send and to receive and modular growth capability.
Further, it is preferred to use a nonblocking medium, one that allows any interconnection that the processors are capable of handling to be made at any time. Such a medium is most versatile and efficient in that, it does not limit the number of interconnections between processors that may be made. It therefore delays the establishment of interprocessor connections the least of any interconnection arrangement. Also, because it allows a plurality of independent connections to exist at a time, such a medium achieves higher communication band with other media. Furthermore, nonblocking media, such as, for example, a crossbar switch, permit direct connection between a source and destination, and therefore, do not suffer from the latency of message or packet passing arrangements typically found in non-crossbar network systems.
Another problem facing bidirectional switching through crossbar switches, is the need for many communication ports within the crossbar system. For example, with a 40-port switch design requiring control wires, at least six wires are required per master port to identify the slave port to which a connection is desired. This implies that 240 bits per switch chip are necessary, which detracts heavily from the wires available for data transmission. In practice, this leads to a system that supports far fewer ports than otherwise is optimal. Another area that is desired to optimize is that of latency. Many switch designs sacrifice latency for connectivity. That is, as more ports are required, there is a large latency or lower band width to connect the systems. This reduces productivity and throughput, as well as slows the overall system operation speed.
Accordingly, what is needed is a crossbar switch that reduces the number of communication wires necessary for intercommunication, as well as maintaining a high degree of connectivity with a minimum overhead. Additionally, what is needed is a networking system that has a very low latency in comparison to prior solutions based upon the interconnection logic between two ports communication one with another. What is further needed is an improved approach at providing on-chip synchronization and broadcasting to minimize overhead.